When testing devices, and particularly electrical devices, it is desirable to place the pin electronics that receive, drive, generate, process or evaluate test signals (i.e., provide test functions) as close as possible to a device under test (DUT). This is because, despite the many techniques for mitigating signal degradation over a signal transmission path, it is usually easier to mitigate signal degradation over a shorter signal path rather than a longer signal path.
Ideally, all of the pin electronics that need to interface with a DUT I/O would be placed very close to the DUT I/O. However, many DUTs have small form factors or high input/output (I/O) densities that make this difficult (or impossible). As a result, the designers of test systems often need to choose between 1) implementing a full spectrum of desired test functions at a location farther from the DUT I/O, or 2) implementing a reduced set of test functions at a location closer to the DUT I/O.